As illustrated in FIG. 11, a typical active matrix liquid crystal display device includes: a display area 101; a plurality of scanning signal lines G; a scanning signal line drive circuit (hereinafter, gate driver) 102 that outputs scanning signals to the respective scanning signal lines G; data signal lines SL orthogonal to the respective scanning signal lines G; and a data signal line drive circuit (hereinafter, source driver) 103 that outputs, to the respective data signal lines SL, data signals corresponding to display signals.
This active matrix liquid crystal display device has n scanning signal lines G and m data signal lines D (n and m indicate the numbers of the lines). The gate driver 102 includes gate driver ICs (GDs) for driving n scanning signal lines G, while the source driver 103 includes source driver ICs (SD) for driving m data signal lines D.
As shown in FIG. 12, the scanning lines G are connected to the respective gates of TFTs (Thin Film Transistors) 104 provided in respective pixels on the display area 101. In a similar manner, the data signal lines SL are connected to the respective sources of the TFTs 104. When a scanning signal line G is active, the TFT 104 connected thereto supplies a data signal to a liquid crystal capacity CL. When the scanning signal line is inactive, an electric charge having been applied to the liquid crystal capacity CL connected to the TFT 104 is maintained.
Incidentally, in recent years there have been liquid crystal display devices adopting wide VGA with 854×480 pixels, in order to support the 16:9 aspect ratio of the screen.
In these wide VGA liquid crystal display devices, the number of the data signal lines SL (i.e. m data signal lines) is equal to 854 pixels×red (R), green (G), and blue (B), and hence m=854×3=2562. When these 2562 data signal lines D are driven using source driver ICs (SD) each can drive 384 data signal lines SL, the number of the required source driver ICs (SD) is 7, because 2562/384=6.7.
7 source driver IDs (SD) each can drive 384 data signal lines D are adopted, so that the number of the data signal lines SL is 2688, as 7×384=2688. As a result, 126 data signal lines are redundant, because 2688−2562=126. Note that, since the source drive ICs (SD) are typically standardized products for VGA (640×480 pixels), it is unrealistic to adopt custom-made source driver ICs (SD) with which no data signal line SL is redundant.
As shown in FIG. 13, these 126 data signal lines SL are provided in the following manner: 126 data signal lines SL as dummies (D) are divided into two groups, and these groups each including 126/2=63 data signal lines SL are provided on the left side of the leftmost source driver IC (SD1) and on the right side of the rightmost source river IC (SD7), respectively. These groups on the right and left sides include identical numbers of the data signal lines SL as the dummies, because, in the case of television, the scanning is carried out both from the right side and the left side, so that the scanning from the right side and the scanning from the left side must be performed on an identical condition. Note that, 63 dummy signals on one side are assigned to R, G, and B, and R, G, and B signals are simultaneously output in one clock. The number of clocks for the dummy signals is therefore 63/3 (R, G, and B)=21.
The following describes a case where image reproduction is performed using the aforesaid source driver ICs (SD1 to SD7). It is noted that the image reproduction on the display area 101 is based on the premise that, data for one horizontal period is stored when a start pulse (SP) is given, and subsequently, at the appearance of a latch pulse (LP), the data is supplied to the display area 101 at a stroke, via the data signal lines SL.
As shown in FIG. 13, a start pulse (SP) for one clock is given for a start, and after clocks D for the dummy signals of the source driver IC (SD1) elapse, the source driver IC (SD1) starts to store a set of display data. Then the source driver ICs (SD2 to SD7) store respective sets of display data. After the last source driver IC (SD7) finishes the storage of the set of display data, a latch pulse (LP) is given and these stored sets of display data for one horizontal period are supplied to the display area 101 at a stroke, via the data signal lines SL.
In the image reproduction method above, a blank period for at least α clocks is required from the finish of the storage of the sets of data for one horizontal period to the start of the storage of the sets of data for the next horizontal period. These a clocks are made up of the following clocks:
clocks C1 from the finish of the storage of the display data to the start of the latch pulse (LP);
clocks C2 from the start of the latch pulse (LP) to the start of the start pulse (SP) of the next line;
clocks C3 from the start of the start pulse (SP) to the start of the output of the dummy signals; and
clocks C4 for the output of the dummy signals.
In the example above, provided that C2=2 clocks and C3=1 clock, C4=D=21 clocks. Therefore, the following equation is formed:
            α      ⁢                          ⁢      clocks        =                            C          ⁢                                          ⁢          1                +                  C          ⁢                                          ⁢          2                +                  C          ⁢                                          ⁢          3                +                  C          ⁢                                          ⁢          4                    ⁢                          ⁢                          =                                    C            ⁢                                                  ⁢            1                    +          2          +          1          +          D                ⁢                                  ⁢                                  =                                            C              ⁢                                                          ⁢              1                        +            2            +            1            +            21                    ⁢                                          ⁢                                          =                                    C              ⁢                                                          ⁢              1                        +            24                                ⁢        
Therefore, a clocks is at least 24 clocks even if C1=0. As a result, the increase of the dummy (D) signal lines results in the prolongation of one horizontal period. In other words, the number of clocks in one horizontal period increases.
To avoid this elongation of one horizontal period, for instance, Patent Document 1 teaches that the clock frequency is increased. However, since the number of clocks in one horizontal period does not decrease even if the clock frequency is increased, this method is ineffective and noncontributory.
To solve this problem, for instance, Japanese Laid-Open Patent Application No. 5-35221/1993 (published on Feb. 12, 1993) discloses the following method shown in FIG. 14: A display area 201 is, for instance, divided into a display area 201a and a display area 201b. In line with this division, source driver ICs (SD1 to SD8) are divided into two groups: the source driver ICs (SD1 to SD4) and the source driver ICs (SD5 to SD8). These two groups of the source driver ICs are driven by two buses BUSA and BUSB through two systems of video signal supply lines 202a and 202b, respectively.
According to this driving method, as shown in FIG. 15(a), the source driver ICs (SD1 to SD4) starts to store respective sets of display data, when a start pulse (SPA) is given. Subsequently, after the data storage by the last source driver IC (SD4) finishes, a latch pulse (LPA) is given, so that the sets of data having been stored in the source driver ICs (SD1 through SD4) are supplied to the display area 201a at a stroke, via the respective data signal lines SL of the bus BUSA.
Simultaneously with the above, as shown in FIG. 15(b), the source driver ICs (SD5 to SD8) start to store respective sets of display data, when the start pulse (SPA) is given. Subsequently, after the data storage by the last source driver IC (SD8) finishes, the latch pulse (LPA) is given, so that the sets of data having been stored in the source driver ICs (SD5 through SD8) are supplied to the display area 201b at a stroke, via the respective data signal lines SL of the bus BUSB.
According to this driving method, image reproduction can be realized by clocks half as much as one horizontal period. For this reason, even if the dummy signal lines are provided on the left side of the source driver IC (SD1) and on the right side of the source driver IC (SD8), the number of clocks does not exceed the number of clocks in one horizontal period.
However, in the liquid crystal display device of Japanese Laid-Open Patent Application No. 5-35221/1993, the source driver ICs are driven using two buses BUSA and BUSB. This requires a circuit dedicated to the drive by these two buses BUSA and BUSB, thereby complicating overall circuitry.